Process for forming semiconductor device isolation regions

Details Process for forming semiconductor device isolation regions Process for forming semiconductor device isolation regions

1991-02-20

1992-05-26

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 40, 437 61, 437 64, 437 69, H01L 21302, H01L 21304, H01L 21306, H01L 2176

Patent

active

051167794

ABSTRACT:
A process for forming a semiconductor device isolation region which comprises:

REFERENCES:
patent: 4546538 (1985-10-01), Suzuki
patent: 4666556 (1987-05-01), Fulton et al.
patent: 4666557 (1987-05-01), Collins et al.
patent: 4671851 (1987-06-01), Beyer et al.
patent: 4876214 (1989-10-01), Yamaguchi et al.
IBM Technical Disclosure Bulletin, vol. 28, No. 6, Nov. 1985, pp. 2583-2584; "Trench Filling Process".
IBM Technical Disclosure Bulletin, vol. 29, No. 3, Aug. 1986, pp. 1240-1242, "Process for Trench Planarization".
"Apractical Trench Isolation Technology with a Novel Planarization Process", pp. 732-735.
"A New Trench Isolation Technology as a Replacement of Locos", pp. 578-581.
"Buries-Oxide Isolation with Etch-Stop (Boxes)"-IEEE Electron Device Letters, vol. 9, No. 2, Feb. 1988-pp. 62-64.
IBM Technical Disclosure Bulletin-vol. 24, No. 7B, Dec. 1981, pp. 3684-3688.
IBM Technical Disclosure Bulletin-vol. 23, No. 11, Apr. 1981, pp. 4917-4919.

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