Static information storage and retrieval – Addressing – Sync/clocking
Patent
1994-06-22
1996-09-17
Zarabian, A.
Static information storage and retrieval
Addressing
Sync/clocking
365190, 36518905, G11C 800
Patent
active
055575820
ABSTRACT:
A semiconductor memory device executes the control of data input/output in accordance with control signals and address signals. The device includes data buses, a memory cell array including a plurality of memory cells, a circuit for selecting a specific memory cell from the memory cells to provide the data buses with cell information data stored in the selected cell and data output control circuit for controlling data output from the memory device, based on at least one control signal provided to the control circuit. The control circuit has an output terminal for outputting the output data, and maintains the terminal at a high-impedance state as long as the cell information provided on the data buses is not supplied to the control circuit.
REFERENCES:
patent: 4922461 (1990-05-01), Hayakawa
Fujitsu Limited
Fujitsu VLSI Limited
Zarabian A.
LandOfFree
Semiconductor memory device inhibiting invalid data from being o does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory device inhibiting invalid data from being o, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device inhibiting invalid data from being o will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-419344