Non-volatile semiconductor memory device with verify mode for ve

Details Non-volatile semiconductor memory device with verify mode for ve Non-volatile semiconductor memory device with verify mode for ve

1995-04-24

1996-09-17

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518525, 36518511, 36518512, G11C 700

Patent

active

055575684

ABSTRACT:
A non-volatile semiconductor memory device includes a flip-flop circuit for holding write data in one of first and second states. A bit line is connected to the flip-flop circuit via a switching element, and a transistor charges the bit line. A non-volatile memory cell, connected to the bit line and having a MOS transistor structure, stores data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode the threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range. A data setting circuit for connects one of first and second signal nodes of the flip-flop circuit to a predetermined potential when the bit line is at the charge potential in the verify mode, thereby setting the flip-flop circuit in the second state irrespective of the state prior to the verify mode.

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Tanaka et al., "A Quick Intelligent Program Architecture for 3V-only NAND-EEPROMs", 1992 Symposium on VLSI Circuits, Digest of Technical Papers, 4 Jun. 1992, IEEE, New York, USA, pp. 20-21.

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