DLL clock signal generating circuit capable of correcting a...

Details DLL clock signal generating circuit capable of correcting a... DLL clock signal generating circuit capable of correcting a...

2008-07-09

2010-06-15

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S175000

Reexamination Certificate

active

07737745

ABSTRACT:
A DLL (Delay Locked Loop) clock signal generating circuit includes a duty correction buffer for receiving a first clock signal and a second clock signal, producing a first internal clock signal and a second internal clock signal, and correcting duty ratios of the first and second internal clock signals based on a reference signal which is controlled by a duty ratio of the first internal clock signal, and an edge trigger unit for a DLL clock signal which has a first level when the first internal clock signal is activated and which has a second level when the second internal clock signal is activated.

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