Semiconductor device with multiple interconnect layers and vias

Details Semiconductor device with multiple interconnect layers and vias Semiconductor device with multiple interconnect layers and vias

2006-01-11

2010-02-16

Gurley, Lynne A. (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S760000, C257S775000, C438S622000, C438S626000, C438S638000

Reexamination Certificate

active

07663240

ABSTRACT:
Mechanical strength and moisture resistance of a multilayer interconnect structure is to be improved. A semiconductor device includes a circuit region and a seal ring region formed around the circuit region, on a semiconductor substrate. The seal ring region includes a plurality of interconnect layers including interconnect lines and a plurality of via layers including a plurality of slit vias stacked on one another, and a pitch between the slit vias in at least one of the via layers (lower or middle layer) is different from a pitch between the slit vias in other via layers (upper layer).

REFERENCES:
patent: 2003/0025191 (2003-02-01), Takeoka et al.
patent: 2004/0084777 (2004-05-01), Yamanoue et al.
patent: 2004/0150070 (2004-08-01), Okada et al.
patent: 2004/0195586 (2004-10-01), Suzuki
patent: 2001-274338 (2001-10-01), None
patent: 2004-134450 (2004-04-01), None
patent: 2004-296843 (2004-10-01), None
patent: 2004-297022 (2004-10-01), None
patent: 2004-304124 (2004-10-01), None
Japanese Patent Office issued a Japanese Office Action dated Oct. 6, 2009, Application No. 2005-020820.

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