Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
2006-08-04
2010-11-02
Pham, Chi H (Department: 2471)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S428000
Reexamination Certificate
active
07826468
ABSTRACT:
In particular embodiments of the present invention, a method for bypassing an output queue structure of a switch is provided. In a particular embodiment, a method for bypassing an output queue structure of a switch includes receiving a packet at an input port of a switch, storing the packet in a memory of the switch, and generating a forwarding request associated with the stored packet and with a particular output port of the switch, the forwarding request identifying the location in the memory of the stored packet. The method also includes determining whether to cause the forwarding request to bypass an output queue structure associated with the particular output port. The method further includes, using the forwarding request, retrieving from the memory the packet associated with the forwarding request and sending the retrieved packet from the particular output port.
REFERENCES:
patent: 5872783 (1999-02-01), Chin
patent: 6327625 (2001-12-01), Wang et al.
patent: 6724779 (2004-04-01), Alleyne et al.
patent: 6766389 (2004-07-01), Hayter et al.
patent: 6912602 (2005-06-01), Sano et al.
patent: 6912637 (2005-06-01), Herbst
patent: 6922408 (2005-07-01), Bloch et al.
patent: 6922749 (2005-07-01), Gil et al.
patent: 6934283 (2005-08-01), Warner
patent: 6941407 (2005-09-01), Shah et al.
patent: 7035255 (2006-04-01), Tzeng
patent: 7039770 (2006-05-01), Chen et al.
patent: 2001/0005369 (2001-06-01), Kloth
patent: 2002/0161923 (2002-10-01), Foster et al.
patent: 2002/0184529 (2002-12-01), Foster et al.
patent: 2003/0131131 (2003-07-01), Yamada et al.
patent: 2004/0158636 (2004-08-01), Nakagawa et al.
patent: 2004/0213237 (2004-10-01), Yasue et al.
patent: 2005/0053006 (2005-03-01), Hongal et al.
patent: 2005/0058149 (2005-03-01), Howe
patent: 2005/0226146 (2005-10-01), Rider
patent: 2006/0227777 (2006-10-01), Shimizu
patent: 2007/0268903 (2007-11-01), Nakagawa
patent: 2007/0268926 (2007-11-01), Nakagawa et al.
patent: 2007/0280104 (2007-12-01), Miyoshi et al.
patent: 2008/0031269 (2008-02-01), Shimizu et al.
patent: 2008/0123525 (2008-05-01), Miyoshi et al.
patent: 1 130 854 (2001-09-01), None
patent: WO 2004/023732 (2004-03-01), None
Shimizu et al., “A Single Chip Shared Memory Switch with Twelve 10Gb Ethernet Ports”, pp. 1-17, Issued Aug. 19, 2003.
Horie et al., “Single-Chip, 10-Gigabit Ethernet Switch LSI”, pp. 206-213, Fujitsu Sci. Tech. J., 42.2, Issued Jun. 2006.
Seifer, “The Switch Book,” Wiley Computer Publishing, ISBN 0-471-34586-5, pp. 1-698, 2000.
IEEE, “Shared and Independent VLAN Learning”, Virtual and Bridged Local Area Networks, IEEE Computer Society, 802.1Q-2005, Annex B, pp. 225-232, IEEE Park Avenue, New York, NY, May 19, 2006.
Minkenberg et al., “A Combined Input and Output Queued Packet-Switched System Based on PRIZMA Switch-on-a-Chip Technology,” IEEE Communications Magazine, pp. 70-71, Dec. 2000.
Sterbenz et al., “High-Speed Networking” A Systematic Approach to High-Bandwidth Low-Latency Communication, 5 pages, 2001.
Choudhury et al., “Dynamic Queue Length Thresholds for Shared-Memory Packet Switches”, IEEE/ACM Transactions on Networking, vol. 6, No. 2, pp. 130-140, Apr. 1998.
Shreedhar et al., “Efficient Fair Queuing Using Deficit Round Robin,” pp. 1-21, Oct. 16, 1995.
Roscoe et al., “Predicate Routing: Enabling Controlled Networking,” ACM SIGCOMM Computer Communications Review, XP-001224681, vol. 33, No. 1, pp. 65-70, Jan. 2003.
EPO European Search Report for Application No./Patent No. 06007587.6-2416, Reference No. 114 663 a/Iga, Applicant:Fujitsu Ltd., 4 pages, mailed Aug. 1, 2006.
Nakagawa et al., “System and Method for Allocating Memory Resources in a Switching Environment,” U.S. Appl. No. 11/419,703, filed May 22, 2006, 42 pages, 5 pps. drawings, 073338.0350.
Nakagawa, “System and Method for Assigning Packets to Output Queues”, U.S. Appl. No. 11/419,713, filed May 22, 2006, 40 pages, 4 pps drawings, 073338.0351.
Miyoshi et al., “System and Method for Filtering Packets in a Switching Environment,” U.S. Appl. No. 11/462,513, filed Aug. 4, 2006, 38 pages, 4 pps. drawings, 073338.0353.
Miyoshi et al., “System and Method for Managing Forwarded Database Resources in a Switching Environment”, U.S. Appl. No. 11/421,679, filed Jun. 1, 2006, 33 pages, 4 pps. drawings, 073338.0354.
Shimizu et al., “Filtering Frames at an Input Port of a Switch”, U.S. Appl. No. 11/278,751, filed Apr. 5, 2006, 24 pages, 3 pps. drawings, 073338.0308.
Nakagawa, “Managing Shared Memory Resources in a High-Speed Switching Environment”, U.S. Appl. No. 10/3600,085, filed Feb. 7, 2003, 40 pages, 5 pps. drawings, 073338.0115.
Nakagawa, “Queuing Packets Written to Memory for Switching”, U.S. Appl. No. 10/360,079, filed Feb. 7, 2003, 37 pages, 4 pps. drawings, 073338.0119.
European Search Report and Office Action, Application No. 07010676.0-1249, 8 pages, Oct. 7, 2007, Oct. 4, 2007.
IEEE Standards, IEEE Standards for Local and Metropolitan Area Network, 802.1Q, May 7, 2003, 11 pages.
Nakagawa Yukihiro
Shimizu Takeshi
Baker & Botts L.L.P.
Fujitsu Limited
Mohebbi Kouroush
Pham Chi H
LandOfFree
System and method for bypassing an output queue structure of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for bypassing an output queue structure of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for bypassing an output queue structure of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4186598