Method for manufacture of integrated semiconductor circuits, in

Details Method for manufacture of integrated semiconductor circuits, in Method for manufacture of integrated semiconductor circuits, in

1980-09-16

1982-10-05

Saba, W. G.

Metal working

Method of mechanical manufacture

Assembling or joining

29571, 29578, 29579, 29580, 148174, 156644, 156653, 156657, 156662, 357 24, 357 59, H01L 2120, H01L 21283

Patent

active

043522378

ABSTRACT:
In an exemplary embodiment, after underetching a first polysilicon layer beneath spaced SiO.sub.2 cover layers to produce pairs of confronting SiO.sub.2 overhangs with gaps therebetween, and providing an insulating layer at the end faces of the spaced poly-Si-1 electrodes formed from the first polysilicon layer, a second polysilicon layer is produced by chemical vapor deposition (CVD) so as to fill the cavities beneath the SiO.sub.2 overhangs via the gaps between each pair of confronting overhangs. The second polysilicon layer is then etched away so as to leave intervening self-adjusting, nonoverlapping poly-Si-2 electrodes formed from the second polysilicon layer with surfaces terminating for example slightly below the upper surfaces of the SiO.sub.2 cover layers. For a center-to-center spacing of poly-Si-1 electrodes of six microns, the SiO.sub.2 overhangs may have an extent (e.g. 0.7 microns) about equal to the electrode layer thickness (e.g. 0.8 microns).

REFERENCES:
patent: 3927468 (1975-12-01), Anthony et al.
patent: 3941630 (1976-03-01), Larrabee
patent: 4035906 (1977-07-01), Tasch et al.
patent: 4055885 (1977-11-01), Takemoto
patent: 4141765 (1979-02-01), Druminski et al.
patent: 4178396 (1979-12-01), Okano et al.
patent: 4240196 (1980-12-01), Jacobs et al.
Browne et al., "Nonoverlapping Gate Charge-Coupling . . . Application", IEEE J. Solid-State Circuits, vol. SC 11, No. 1, Feb. 1976, pp. 203-207.

Affiliated with

Also associated with

Rating

Method for manufacture of integrated semiconductor circuits, in does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for manufacture of integrated semiconductor circuits, in , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacture of integrated semiconductor circuits, in will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-418645