Method and system for pipeline reduction

Details Method and system for pipeline reduction Method and system for pipeline reduction

2001-12-20

2010-11-30

Li, Aimee J (Department: 2183)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

C712S219000

Reexamination Certificate

active

07844799

ABSTRACT:
A method and system for operating a high frequency out-of-order processor with increased pipeline length. A new scheme is disclosed to reduce the pipeline by the detection and exploitation of so called “no dependency” for an instruction. A “no dependency” signal tells that all required source data is available for the instruction at least one cycle before the source data valid bit(s) are inserted into the issue queue. Therefore, one or more stages of the pipeline are bypassed.

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