Synchronous semiconductor memory device

Details Synchronous semiconductor memory device Synchronous semiconductor memory device

2008-02-26

2010-06-08

Phung, Anh (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S240000

Reexamination Certificate

active

07733739

ABSTRACT:
A synchronous semiconductor memory device of the present invention includes: an operation controller for outputting a column active sense pulse in response to a column address and a column command signal; a shift register controller, activated in response to the column active sense pulse, for dividing a clock signal by N to thereby output a divided clock signal, N being a positive integer greater than 1; a plurality of shift registers connected in series and synchronized with the divided clock signal, wherein each shift register transmits the column active sense pulse to the next shift register; and a column active control signal generator for logically combining outputs of the shift registers to thereby generate a column active control signal.

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