Multi-chip semiconductor package

Details Multi-chip semiconductor package Multi-chip semiconductor package

2009-01-20

2010-12-07

Clark, S. V (Department: 2823)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C438S107000

Reexamination Certificate

active

07846773

ABSTRACT:
Semiconductor packages that contain multiple stacked chips and methods for making such semiconductor packages are described. The semiconductor packages contain a full land pad array and multiple chips that are stacked vertically. Some of the chips are separated by routing leads which are connected to the land pad array. The chips can be directly connected to an inner part of the land pad array and a second and third chip are respectively connected to the middle and outer part of the land pad array through the routing leads that are connected to solder balls. The semiconductor packages therefore have a high input/output capability with a small package footprint, and a flexible routing capability. Other embodiments are also described.

REFERENCES:
patent: 6258626 (2001-07-01), Wang et al.
patent: 7550680 (2009-06-01), Pendse
patent: 7675153 (2010-03-01), Kurosawa et al.
patent: 7709944 (2010-05-01), Kuan et al.
patent: 7723839 (2010-05-01), Yano et al.

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