Test apparatus for electronic assemblies employing a microproces

Details Test apparatus for electronic assemblies employing a microproces Test apparatus for electronic assemblies employing a microproces

1981-06-05

1984-06-19

Malzahn, David H.

Excavating

324 73R, G06F 1122

Patent

active

044556543

ABSTRACT:
A test system for functionally testing and troubleshooting microprocessor-based systems and assemblies is disclosed wherein the test system is connected in place of the microprocessor circuit of the unit being tested (UUT). The test system is itself a microprocessor-based system and includes a microprocessor circuit which is supplied with the UUT clock signal and is the same type of microprocessor circuit as is utilized by the UUT. The test system periodically switches this microprocessor into signal communication with the UUT for a single UUT bus cycle to perform UUT read or write operations. During remaining time periods, the test system microprocessor circuit is in signal communication with the remaining portion of the test system to analyze data obtained from the UUT bus during the previous UUT write or read operation and to establish the signals to be used in the next UUT write or read operation. Various test sequences are provided for testing the UUT bus, RAM, ROM, and write-responsive I/O registers. In addition, a mode of operation is provided wherein the test system interrogates a fully functional assembly of the type to be tested to derive a memory map and test parameters that permit the test system to perform RAM, ROM, and I/O tests without prior knowledge of the UUT operational sequence or allocation of address space. A test probe provides a visual indication that the logic level at a monitored circuit node is high, low, invalid, or is a sequence of pulses of all three logic levels. The test probe also provides for injection of logical high pulses, logical low pulses or an alternating pulse sequence of high and low pulses. Probe logic level detection and pulse injection can be asynchronous or can be selectively synchronized so that logic level detection or pulse injection occurs with each UUT write or read operation.

REFERENCES:
patent: 4125763 (1978-11-01), Drubing et al.
patent: 4192451 (1980-03-01), Swerling et al.
patent: 4228537 (1980-10-01), Heackels et al.
patent: 4300207 (1981-11-01), Eivers et al.
patent: 4339801 (1982-07-01), Hosaka et al.
Anderson et al. "Processor-Based Tester Goes on Site to Isolate Board Faults Automatically" Electronics May 11, 1978, pp. 111-117.

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