Histogram generation with configurable memory

Details Histogram generation with configurable memory Histogram generation with configurable memory

2007-10-22

2010-11-09

Barbee, Manuel L (Department: 2857)

Data processing: measuring, calibrating, or testing

Testing system

Of circuit

C702S180000

Reexamination Certificate

active

07831404

ABSTRACT:
The configuration and utilization of multiple memories is disclosed to efficiently gather histogram data for either multiple devices or single devices. Each memory can be configured depending on the number of ADCs to be tested. Rather than utilizing a separate histogram engine for each ADC, or duplicate memories to test each ADC, the memory of each histogram engine can be used either for a single ADC having a large or otherwise substantial sample width, or for multiple ADCs, each having a smaller sample width. To accomplish this, the memory is partitioned into multiple segments using address decoding such that a single ADC can use all of the segments for histogram data collection, while multiple ADCs can each use one of the segments for histogram data collection.

REFERENCES:
patent: 5063383 (1991-11-01), Bobba
patent: 5294926 (1994-03-01), Corcoran

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