Self-checking, dual railed, leading edge synchronizer

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371 47, 371 63, G06F 900

Patent

active

047003464

ABSTRACT:
A digital logic circuit and method for synchronizing the leading edges skewed true-complement signal pair. The circuit is comprised of two similar, interconnected circuit halves, each of which includes three D flip-flop stages. The outputs from the second D flip-flop stages from the two circuit halves are applied to the two inputs of two identical logic gates, such that the signal pair is synchronously transmitted to a pair of output gates through a third D flip-flop stage in each circuit half. The second D flip-flop stages also prevent metastable states from reaching the synchronizer output. Metastable states may result if the input setup time is violated for the first D flip-flop stages. The third D flip-flop stage in each circuit half also eliminates any signal irregularities generated in the logic circuitry from appearing on the synchronizer output lines. The circuit is self-checking in that any single fault in the input signals or in the synchronizer circuit itself will result in the synchronizer output pair not having a true complement relationship.

REFERENCES:
patent: 4328583 (1982-05-01), Stodola
patent: 4342112 (1982-07-01), Stodola
patent: 4408327 (1983-10-01), Wahl et al.
patent: 4520483 (1985-05-01), Arita et al.
patent: 4551836 (1985-11-01), Parikh
patent: 4589066 (1986-05-01), Lam et al.
Computer System Architecture, by M. Morris Mano, p. 411, Section 11-3: "11-3 Asynchronous Serial Interface", 1976.

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