Semiconductor device and method of manufacturing the same

Details Semiconductor device and method of manufacturing the same Semiconductor device and method of manufacturing the same

2007-12-21

2010-06-01

Blum, David S (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S774000, C257SE21495, C257SE23141

Reexamination Certificate

active

07728434

ABSTRACT:
Aimed at improving adhesiveness between upper and lower interconnects in semiconductor devices, a semiconductor device of the present invention includes a second dielectric multi-layered film formed on a substrate, and containing a lower interconnect; a first dielectric multi-layered film formed on the second dielectric multi-layered film, and having a recess; an MOx film formed on the inner wall of the recess, and containing a metal M and oxygen as major components; an M film formed on the MOx film, and containing the M as a major component; and an electric conductor formed on the M film so as to fill the recess, and containing Cu as a major component, wherein the surficial portion of the interconnect fallen straight under the bottom of the recess has an oxygen concentration of 1% or smaller.

REFERENCES:
patent: 2008/0174018 (2008-07-01), Ueda
patent: 2009/0206485 (2009-08-01), Yang et al.
patent: 2000-269455 (2000-09-01), None
patent: 2002-075994 (2002-03-01), None
patent: 2005-236285 (2005-09-01), None
patent: 2005-347510 (2005-12-01), None
patent: 2006-005305 (2006-01-01), None
patent: 2006-019325 (2006-01-01), None
Ohashi et al., “Robust Porour MSQ (k=2.3, E=12 GPa) for Low-temperature (<350° C.) Cu/Low-k Integration using ArF Resist Mask Process”, 2003, pp. 857-860.
Matsunaga et al., “BEOL Process Integration Technology for 45nm Node Porous Low-k/Copper Interconnects”, 3 pages, 2005.

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