Reset circuit and system having reset circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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Details

C327S198000

Reexamination Certificate

active

07659758

ABSTRACT:
In a power-on detection circuit, a first connection node at which a first divided voltage is generated is connected to a second power supply line during activation of a power-down detection signal. Inactivation timing of the power-down detection signal is set earlier than an activation timing of a power-on detection signal. Therefore, the first transistor whose gate is connected to the first connection node is certainly turned off in the first half of a power-on period, which prevents the power-on detection signal from being activated during the power-on period. Further, a leak current flowing through the first transistor is reduced. In the second half of the power-on period, the power-on detection signal is certainly generated using the first divided voltage generated by the first dividing circuit. Thus, operating a reset circuit without malfunction and normally outputting a reset signal is possible disregarding behavior of a power supply voltage at power-on.

REFERENCES:
patent: 7425854 (2008-09-01), Suzuki
patent: 7545186 (2009-06-01), Suzuki et al.
patent: 2005/0275437 (2005-12-01), Suzuki et al.
patent: 2007/0159222 (2007-07-01), Ogai et al.

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