Clamping circuit and digital camera system having the...

Television – Camera – system and detail – Combined image signal generator and general image signal...

Reexamination Certificate

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Details

C348S689000, C327S309000, C327S312000, C327S316000

Reexamination Certificate

active

07728888

ABSTRACT:
A clamping circuit including: a subtracter for subtracting a clamping correction voltage from an input analog voltage signal; A/D converter for converting an analog voltage signal from the subtracter into a digital voltage signal of M bits; a potential difference detection circuit for detecting a potential difference between a digital voltage signal outputted from the A/D converter and a previously set clamping voltage; D/A converter for converting a digital signal of N (N<M) bits within the digital signal of M bits representing a potential difference outputted from the potential difference detection circuit into an analog signal; an adjusting voltage generation circuit for generating an adjusting voltage based on a potential difference outputted from the potential difference detection circuit and a threshold voltage set with respect to the potential difference; and an adder for adding together an output from the D/A converter and an adjusting voltage outputted from the adjusting voltage generation circuit to generate the clamping correction voltage.

REFERENCES:
patent: 4625240 (1986-11-01), Yablonski et al.
patent: 5032740 (1991-07-01), Kannegundla
patent: 5296929 (1994-03-01), Morimoto
patent: 5319450 (1994-06-01), Tamayama et al.
patent: 5477183 (1995-12-01), Hayes
patent: 6580465 (2003-06-01), Sato
patent: 7468760 (2008-12-01), Huang et al.
patent: 7646412 (2010-01-01), Hisamatsu et al.
patent: 2004/0008270 (2004-01-01), Hisamatsu et al.
patent: 2004/0130375 (2004-07-01), Tachibana
patent: 2004/0189839 (2004-09-01), McDermott
patent: 2005/0237402 (2005-10-01), Sase et al.
patent: 2007/0247533 (2007-10-01), Hisamatsu et al.
patent: 06046287 (1994-02-01), None

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