Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reissue Patent
2007-11-19
2010-12-07
Dickey, Thomas L (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S758000, C257S759000, C257S760000, C257S761000, C257S762000, C257S763000, C257S764000, C257S765000, C257S915000
Reissue Patent
active
RE041980
ABSTRACT:
A plurality of metal wires are formed on an underlying interlayer insulating film. Areas among the metal wires are filled with a buried insulating film of a silicon oxide film with a small dielectric constant (i.e., a first dielectric film), and thus, a parasitic capacitance of the metal wires can be decreased. On the buried insulating film, a passivation film of a silicon nitride film with high moisture absorption resistance (i.e., a second dielectric film) is formed, and thus, a coverage defect can be avoided. A bonding pad is buried in an opening formed in a part of a surface protecting film including the buried insulating film and the passivation film, so as not to expose the buried insulating film within the opening. Thus, moisture absorption through the opening can be prevented. In this manner, the invention provides a semiconductor device which has a small parasitic capacitance in an area with a small pitch between the metal wires and is free from a coverage defect as well as the moisture absorption through the opening for the bonding pad, and a method of manufacturing the semiconductor device.
REFERENCES:
patent: 4761386 (1988-08-01), Buynoski
patent: 5136364 (1992-08-01), Byre
patent: 5371047 (1994-12-01), Greco
patent: 5399530 (1995-03-01), Kenmotsu
patent: 5445994 (1995-08-01), Gilton
patent: 5457073 (1995-10-01), Ouellet
patent: 5472913 (1995-12-01), Havemann
patent: 5554305 (1996-09-01), Wojnarowski
patent: 5572737 (1996-11-01), Valice
patent: 5731584 (1998-03-01), Beyne
patent: 5746868 (1998-05-01), Abe
patent: 5785236 (1998-07-01), Cheung et al.
patent: 5804259 (1998-09-01), Robles
patent: 5807787 (1998-09-01), Fu
patent: 5849632 (1998-12-01), Tuttle et al.
patent: 5854127 (1998-12-01), Pan
patent: 5856707 (1999-01-01), Sardella
patent: 5874779 (1999-02-01), Matsuno
patent: 5900668 (1999-05-01), Wollesen
patent: 6037215 (2000-03-01), Lee
patent: RE39932 (2007-12-01), Yabu et al.
patent: 0514888 (1992-11-01), None
patent: 0825646 (1998-02-01), None
patent: 58-122447 (1983-08-01), None
patent: 62128128 (1987-06-01), None
patent: 62-224037 (1987-10-01), None
patent: 62-242331 (1987-10-01), None
patent: 4-58531 (1992-02-01), None
patent: 4-179246 (1992-06-01), None
patent: 5-198572 (1993-06-01), None
patent: 7-312633 (1993-10-01), None
patent: 6-112265 (1994-04-01), None
patent: 6-318590 (1994-11-01), None
patent: 07-130737 (1995-05-01), None
patent: 9-120963 (1997-02-01), None
patent: 9-283554 (1997-10-01), None
patent: WO 96/19826 (1996-06-01), None
Construction Analysis, “IBM Power PC 601 RISC Microprocessor”, Report Number: SUB 9308-02 © by Integrated Circuit Engineering Corporation (ICE).
Segawa Mizuki
Yabu Toshiki
Dickey Thomas L
McDermott Will & Emery LLP
Panasonic Corporation
LandOfFree
Semiconductor interconnect formed over an insulation and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor interconnect formed over an insulation and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor interconnect formed over an insulation and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4150739