Thread manager to control an array of processing elements

Electrical computers and digital processing systems: processing – Processing architecture – Array processor

Reexamination Certificate

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C712S016000, C712S022000

Reexamination Certificate

active

07627736

ABSTRACT:
A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array. The apparatus is operable to process multiple instructions streams in parallel with one another.

REFERENCES:
patent: 4229790 (1980-10-01), Gilliland et al.
patent: 4316245 (1982-02-01), Luu et al.
patent: 4374409 (1983-02-01), Bienvenu et al.
patent: 4395757 (1983-07-01), Bienvenu et al.
patent: 4435758 (1984-03-01), Lorie et al.
patent: 4484273 (1984-11-01), Stiffler et al.
patent: 4538226 (1985-08-01), Hori
patent: 4590465 (1986-05-01), Fuchs
patent: 4602328 (1986-07-01), Finger et al.
patent: 4739476 (1988-04-01), Fiduccia
patent: 4754398 (1988-06-01), Pribnow
patent: 4835729 (1989-05-01), Morton
patent: 4885715 (1989-12-01), Evans et al.
patent: 4907148 (1990-03-01), Morton
patent: 4939638 (1990-07-01), Stephenson et al.
patent: 4985832 (1991-01-01), Grondalski
patent: 5038282 (1991-08-01), Gilbert et al.
patent: 5050065 (1991-09-01), Dartois et al.
patent: 5127104 (1992-06-01), Dennis
patent: 5129077 (1992-07-01), Hillis
patent: 5151969 (1992-09-01), Petsche
patent: 5159686 (1992-10-01), Chastain et al.
patent: 5165023 (1992-11-01), Gifford
patent: 5175858 (1992-12-01), Hammerstrom
patent: 5230079 (1993-07-01), Grondalski
patent: 5247689 (1993-09-01), Ewert
patent: 5276886 (1994-01-01), Dror
patent: 5276895 (1994-01-01), Grondalski
patent: 5371896 (1994-12-01), Gove et al.
patent: 5404478 (1995-04-01), Arai et al.
patent: 5408671 (1995-04-01), Tanaka
patent: 5437045 (1995-07-01), Davies
patent: 5475856 (1995-12-01), Kogge
patent: 5522080 (1996-05-01), Harney
patent: 5535410 (1996-07-01), Watanabe et al.
patent: 5606683 (1997-02-01), Riordan
patent: 5634107 (1997-05-01), Yumoto et al.
patent: 5652833 (1997-07-01), Takizawa et al.
patent: 5652872 (1997-07-01), Richter et al.
patent: 5717943 (1998-02-01), Barker et al.
patent: 5717947 (1998-02-01), Gallup et al.
patent: 5752031 (1998-05-01), Cutler et al.
patent: 5752068 (1998-05-01), Gilbert
patent: 5765011 (1998-06-01), Wilkinson et al.
patent: 5796385 (1998-08-01), Rich
patent: 5808690 (1998-09-01), Rich
patent: 5815723 (1998-09-01), Wilkinson et al.
patent: 5828894 (1998-10-01), Wilkinson
patent: 5831625 (1998-11-01), Rich et al.
patent: 5850489 (1998-12-01), Rich
patent: 5892517 (1999-04-01), Rich
patent: 5923338 (1999-07-01), Rich
patent: 5933131 (1999-08-01), Rich
patent: 5949426 (1999-09-01), Rich
patent: 5978838 (1999-11-01), Mohamed et al.
patent: 6104842 (2000-08-01), Rich
patent: 6108460 (2000-08-01), Rich
patent: 6266759 (2001-07-01), Birrittella
patent: 6308252 (2001-10-01), Agarwal et al.
patent: 035647 (1981-09-01), None
patent: 113612 (1984-07-01), None
patent: 268342 (1988-05-01), None
patent: 277262 (1988-08-01), None
patent: 314277 (1989-05-01), None
patent: 328721 (1989-08-01), None
patent: 351556 (1990-01-01), None
patent: 380098 (1990-08-01), None
patent: 422965 (1991-04-01), None
patent: 0428327 (1991-05-01), None
patent: 447146 (1991-09-01), None
patent: 463721 (1992-01-01), None
patent: 543560 (1993-05-01), None
patent: 544127 (1993-06-01), None
patent: 0570950 (1993-11-01), None
patent: 570952 (1993-11-01), None
patent: 588341 (1994-03-01), None
patent: 602909 (1994-06-01), None
patent: 638867 (1995-02-01), None
patent: 638868 (1995-02-01), None
patent: 690384 (1996-01-01), None
patent: 696001 (1996-02-01), None
patent: 726529 (1996-08-01), None
patent: 973099 (2000-01-01), None
patent: 2062915 (1981-05-01), None
patent: 2074351 (1981-10-01), None
patent: 2078407 (1982-01-01), None
patent: 2216306 (1989-10-01), None
patent: 2273377 (1994-06-01), None
patent: 2286909 (1995-08-01), None
patent: 2287559 (1995-09-01), None
patent: 03132861 (1991-06-01), None
patent: 070013956 (1995-01-01), None
patent: 090288652 (1997-11-01), None
patent: WO 90/16031 (1990-12-01), None
patent: WO 91/10200 (1991-07-01), None
patent: WO 92/07335 (1992-04-01), None
patent: WO 92/15061 (1992-09-01), None
patent: WO 94/11815 (1994-05-01), None
patent: WO 96/08778 (1996-03-01), None
patent: WO 96/41250 (1996-12-01), None
patent: WO 98/35301 (1998-08-01), None
patent: WO 99/19807 (1999-04-01), None
patent: WO 99/53411 (1999-10-01), None
patent: WO 99/53412 (1999-10-01), None
patent: WO 99/53413 (1999-10-01), None
patent: WO 00/22515 (2000-04-01), None
patent: WO 00/62182 (2000-10-01), None
Espasa, et al.; “Simultaneous Multithreaded Vector Architecture: Merging ILP and DLP for High Performance”; 1997; IEEE, pp. 350-357.
Espasa, et al.; “Exploiting Instruction-and Data-Level Parallelism”; 1997, IEEE, pp. 20-27.
Espasa, et al; “Multithreaded Vector Architectures”; 1997; IEEE, pp. 237-248.
Harrell, et al.; “Graphics Rendering Architecture for a High Performance Desktop Workstation”; 1993; ACM, pp. 93-100.
Limousin, et al.; “Improving 3D Geometry Transformations on a Simultaneous Multithreaded SIMD Processor”; 2001, ACM, pp. 236-245.
Salami, et al.; “An Evaluation of Different DLP Alternatives for the Embedded Media Domain”; Nov. 1999; 1st Workshop on Media Processors and DSPs (MPDSP-1), 10 pages.
Weems, Charles; “Asynchronous SIMD: An Architectural Concept for High Performance Image Processing”; Oct. 20-22, 1997; Proceedings fourth IEEE Int'l Workshop on Computer Architecture for Machine Preception, pp. 235-242.
Jeng et al; “A Fault-tolerant multistage interconnection network for multiprocessor systems using dynamic redundancy”; 6th International Conference on Distributed Computing Systems Proceedings; pp. 70-77; see INSPEC abstract No. C86052412.
Bailey, David; “Anatomy of a DOS Extender”; Jul. 1989; EXE Magazine, vol. 4, Issue 2, pp. 56-59.
Bursky, Dave; “ISSCC: Digital Technology”; Feb. 21, 1994; Electronic Design, pp. 69-83.
Eyles, et al.: “PixelFlow™ The Realization”; Hewlett-Packard Co. Chapel Hill Graphics Lab and Dept. of Computer Science Univ. of North Carolina.
Eyles, et al.; “PixelFlow™ Rasterizer Functional Description”; Nov. 20, 1997; Dept. of Computer Science Univ. of North Carolina at Chapel Hill.
Petzold, Charles; Environments “OS/2 and the 386: They Should Have Been Made for Each Other”; Jan. 16, 1990; PC Magazine, pp. 303-308.
Rennels, David A.; “On Implementing Fault-Tolerance in Binary Hypercubes”; 1986; IEEEE, International Symposium on Fault-Tolerant Computer Systems (FTCS), vol. SYMP Pt. 16, pp. 344-349.
Sernec, et al.; “Multithreaded Systolic/SIMD DSP Array Processor—MUS2DAP”; Nov. 3-5, 1997; IEEE Workshop on Signal Processing Systems, pp. 448-457.
Shigei, et al; “On Efficient Spare Arrangements and an Algorithm with Relocating Spares for Reconfiguring Processor Arrays”; Jun. 1997; IEICE Trans. Fundamentals, vo. E80-A, No. 6pp. 988-995.
Shu, et al.; “A Reliable Design of Parallel Processor Systems*”; 1987; Proceedings of the 1987 International Conference on Parallel Processing; pp. 882-884.
Tucker, et al.; “Architecture and Applications of the Connection Machine”; Aug. 1988; Computer—IEEE Computer Society, vo. 21, part 8, pp. 26-38.

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