Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2008-02-19
2009-12-08
Mai, Son L (Department: 2827)
Static information storage and retrieval
Interconnection arrangements
C365S051000
Reexamination Certificate
active
07630224
ABSTRACT:
A semiconductor integrated circuit device includes a memory macro and M (M is an integer more than 1) passage wirings. The memory macro includes a memory cell array comprising memory cells which are arranged in a matrix, digit line pairs connected with the memory cells and extending in a column direction, and a column peripheral circuit connected with the digit line pairs and comprising a sense amplifier circuit. The M (M is an integer more than 1) passage wirings are arranged to extend in a row direction orthogonal to the digit line pairs. The arrangement of the M passage lines above the column peripheral circuit is forbidden.
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Mai Son L
NEC Electronics Corporation
Young & Thompson
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