Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
2007-04-19
2009-11-17
Donovan, Lincoln (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S199000, C327S201000
Reexamination Certificate
active
07619455
ABSTRACT:
By adjusting a register's capturing clock edge timing so that the register captures data when the data returns to a correct state, the register may be protected against DSET upsets. If a data glitch occurs near the clock edge, the valid time at the register output is increased (CLK to Q). This valid time increase occurs when the presence of a DSET transient is detected near the clock edge.
REFERENCES:
patent: 4775840 (1988-10-01), Ohmori et al.
patent: 5504703 (1996-04-01), Bansal
patent: 5896299 (1999-04-01), Ginetti et al.
patent: 6127864 (2000-10-01), Mavis et al.
patent: 6239616 (2001-05-01), Churcher et al.
patent: 6326809 (2001-12-01), Gambles et al.
patent: 6356101 (2002-03-01), Erstad
patent: 6362676 (2002-03-01), Hoffman
patent: 6629276 (2003-09-01), Hoffman et al.
patent: 6972607 (2005-12-01), Chen et al.
patent: 7142004 (2006-11-01), Calrson
patent: 2001/0048341 (2001-12-01), Chakravarthy
patent: 2006/0119379 (2006-06-01), Carlson
patent: 2006/0119410 (2006-06-01), Carlson
patent: 2006/0267653 (2006-11-01), Fulkerson
patent: 0 135 893 (1984-09-01), None
patent: WO 01/10026 (2001-02-01), None
W. Wang, “RC Hardened FPGA Configuration SRAM Cell Design,” Electronic Letters, Apr. 29, 2004, vol. 40, No. 9.
Mavis, David G., et al. “Soft Error Rate Mitigation Techniques for Modern Microcircuits,” IEEE 02CH37320, 40thAnnual International Reliability Physics Symposium, Dallas, Texas 2002.
Mongkolkachit et al., “Design Technique for Mitigation of Alpha-Particle-Induced Single-Event Transients in Combinational Logic,” IEEE Transactions on Device and Materials Reliability, vol. 3, No. 3, Sep. 2003..
Benedetto et al., “Heavy Ion-Induced Digital Single-Event Transients in Deep Submicron Processes,” IEEE Transactions on Nuclear Science, vol. 51, No. 6, Dec. 2004.
Gadlage et al., “Single Event Transient Pulsewidths in Digital Microcircuits,” IEEE Transactions on Nuclear Science, vol. 51, No. 6, Dec. 2004.
Benedetto et al., “Variation of Digital Set Pulse Widths and the Implications for Single Event Hardening of Advanced CMOS Processes,” IEEE Transactions on Nuclear Science, vol. 52, No. 6, Dec. 2005.
Balasubramanian et al., “RHBD Techniques for Mitigating Effects of Single-Event Hits Using Guard-Gates,” IEEE Transactions on Nuclear Science, vol. 52, No. 6, Dec. 2005.
Wang et al., “Edge Triggered Pulse Latch Design with Delayed Latching Edge for Radiation Hardened Application,” IEEE Transactions on Nuclear Science, vol. 51, No. 6, Dec. 2004.
Eaton et al., “Single Event Transient Pulsewidth Measurements Using a Variable Temporal Latch Technique,” IEEE Transactions on Nuclear Science, vol. 51, No. 6, Dec. 2004.
HX5000 ASIC Platform S150 (150 nm) ASICs, Honeywell International Inc., Aug. 2006.
Mavis, David G. “Single Event Transient Phenomena—Challenges and Solutions,” 2002 Microelectronics Reliability and Qualification Workshop Dec. 3-4, 2002. DTRA, Defense Threat Reduction Agency.
Mavis et al., “SEU and Set Mitigation Techniques for FPGA Circuit and Configuration Bit Storage Design,” Sep. 26-28, 2000. MRC Microelectronics, MAPLD-2000, www.mrcmicroe.com.
European Search Report for 08103600.6-2215 dated Oct. 14, 2008.
Carlson Roy M.
Erstad David O.
Donovan Lincoln
Honeywell International , Inc.
Rojas Daniel
Shumaker & Sieffert P.A.
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