Cache miss prediction method and apparatus for use with a paged

Details Cache miss prediction method and apparatus for use with a paged Cache miss prediction method and apparatus for use with a paged

1992-07-29

1995-09-12

Elmore, Reba I.

Boots, shoes, and leggings

36424342, 36496422, 395452, 395411, 395414, G06F 1202

Patent

active

054505615

ABSTRACT:
In a data processing system which employs a cache memory feature, a method and exemplary special purpose apparatus for practicing the method are disclosed to lower the cache miss ratio for called operands. Recent cache misses are stored in a first in, first out miss stack, and the stored addresses are searched for displacement patterns thereamong. Any detected pattern is then employed to predict a succeeding cache miss by prefetching from main memory the signal identified by the predictive address. The apparatus for performing this task is preferably hard wired for speed purposes and includes subtraction circuits for evaluating variously displaced addresses in the miss stack and comparator circuits for determining if the outputs from at least two subtraction circuits are the same indicating a pattern yielding information which can be combined with an address in the stack to develop a predictive address. The efficiency of the apparatus operating in an environment incorporating a paged main memory is improved, according to the invention, by the addition of logic circuitry which serves to inhibit prefetch if a page boundary would be encountered.

REFERENCES:
patent: 5023776 (1991-06-01), Gregor
patent: 5125083 (1992-06-01), Fite et al.
Patent Abstracts of Japan, vol. 011, No. 226 (p-598) 23 Jul. 1987; JP-A-62 040554 21 Feb. 1987.
European Search Report for corresponding EPO patent application 93103845, transmitted in a communication dated 02-06-1993.

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