Expanded address bus system for providing address signals to exp

Details Expanded address bus system for providing address signals to exp Expanded address bus system for providing address signals to exp

1995-01-25

1995-09-12

Chan, Eddie P.

Boots, shoes, and leggings

364DIG2, 3649402, 36492793, 36492792, 3649294, 395410, 395307, G06F 1300

Patent

active

054505526

ABSTRACT:
An expanded address bus system includes an address decoder for continuously assigning an address to a specific expanded address bus during an access, and access enable signal latch circuit for latching an output from the address decoder during the access, an address latch circuit for latching an address during an access of an address area decoded by the address decoder, an address latch control circuit for generating an address latch timing for the address latch circuit, and a plurality of selectors for selecting an output from the address enable signal latch circuit or the bus access enable signal on the address bus to supply the selected signal to a plurality of expanded slots.

REFERENCES:
patent: 4545010 (1985-10-01), Salas et al.
patent: 4691282 (1987-09-01), Kinoshita

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