Method for controlling parallelism between probe card and...

Details Method for controlling parallelism between probe card and... Method for controlling parallelism between probe card and...

2006-09-08

2009-02-03

Nguyen, Ha Tran T (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

Reexamination Certificate

active

07486089

ABSTRACT:
In a method for controlling a parallelism between a probe card having a number of probe pins and a mounting table, first, among the probe pins, one or more probe pins corresponding to each of plural distinct locations on an X-Y coordinate system whose origin lies at a probe center are selected. Then, a tip of each of the selected probe pins is detected to obtain position coordinates (X,Y,Z) thereof. Thereafter, a specific point on each of connection lines connecting tips of neighboring selected probe pins is selected and their position coordinates on the connection lines are calculated, wherein the position coordinates of the specific points are set as position coordinates (X,Y,Z) of tips of imaginary probe pins. Subsequently, the parallelism between the probe card and the mounting table based on the position coordinates (X,Y,Z) of the tips of the imaginary probe pins is adjusted.

REFERENCES:
patent: 5861759 (1999-01-01), Bialobrodski et al.
patent: 6963208 (2005-11-01), Fukasawa et al.

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