Memory organization in a switching device

Details Memory organization in a switching device Memory organization in a switching device

2005-09-15

2009-06-09

Moe, Aung S (Department: 2416)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S351000, C370S352000, C370S353000, C370S354000, C370S395100, C370S395600, C370S395700, C370S395310, C370S395530, C370S395610, C370S396000, C370S397000, C370S401000, C370S412000, C370S413000, C370S414000, C370S415000, C370S416000, C370S418000, C370S428000, C370S429000, C370S442000

Reexamination Certificate

active

07545808

ABSTRACT:
A network device switches variable length data units from a source to a destination in a network. An input port receives the variable length data unit and a divider divides the variable length data unit into uniform length data units for temporary storage in the network device. A distributed memory includes a plurality of physically separated memory banks addressable using a single virtual address space and an input switch streams the uniform length data units across the memory banks based on the virtual address space. The network device further includes an output switch for extracting the uniform length data units from the distributed memory by using addresses of the uniform length data units within the virtual address space. The output switch reassembles the uniform length data units to reconstruct the variable length data unit. An output port receives the variable length data unit and transfers the variable length data unit to the destination.

REFERENCES:
patent: 4058672 (1977-11-01), Crager et al.
patent: 4596010 (1986-06-01), Beckner et al.
patent: 4884264 (1989-11-01), Servel et al.
patent: 4885744 (1989-12-01), Lespagnol et al.
patent: 4926416 (1990-05-01), Weik
patent: 4933932 (1990-06-01), Quinquis et al.
patent: 4947388 (1990-08-01), Kuwahara et al.
patent: 5155834 (1992-10-01), Ryan et al.
patent: 5214639 (1993-05-01), Herion
patent: 5293597 (1994-03-01), Jensen et al.
patent: 5448702 (1995-09-01), Garcia, Jr. et al.
patent: 5457687 (1995-10-01), Newman
patent: 5491694 (1996-02-01), Oliver et al.
patent: 5521910 (1996-05-01), Matthews
patent: 5521915 (1996-05-01), Dieudonne et al.
patent: 5668968 (1997-09-01), Wu
patent: 5689505 (1997-11-01), Chiussi et al.
patent: 5796944 (1998-08-01), Hill et al.
patent: 5802052 (1998-09-01), Venkataraman
patent: 5872787 (1999-02-01), Cooperman et al.
patent: 5905725 (1999-05-01), Sindhu et al.
patent: 5909440 (1999-06-01), Ferguson et al.
patent: 5956751 (1999-09-01), Lai
patent: 6201813 (2001-03-01), Klausmeier et al.
patent: 6493347 (2002-12-01), Sindhu et al.
patent: 7116660 (2006-10-01), Sindhu et al.
Arpaci, Multu, Copeland, John. A.,Buffer Management For Shared-Memory ATM Switches, IEEE Communications Surveys & Tutorials, First Quarter 2000, pp. 2-10, vol. 3, No. 1.
Verman, Sanjeev,ATM Switch Architectures, A Report in The Department of Electrical and Computer Engineering, Concordia University, Montral, Quebec, Canada, Aug. 1994, pp. 1-81.

Affiliated with

Also associated with

Rating

Memory organization in a switching device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory organization in a switching device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory organization in a switching device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4130463