Process for fabricating a flash EEPROM

Details Process for fabricating a flash EEPROM Process for fabricating a flash EEPROM

1995-11-13

1996-09-17

Wilczewski, Mary

Fishing, trapping, and vermin destroying

437 69, 257316, H01L 218247

Patent

active

055567991

ABSTRACT:
A process for fabricating a flash EEPROM device in a semiconductor substrate. The flash EEPROM device includes a number of memory cells each built around a transistor. A shielding layer is first formed over the surface of the substrate extending in a first direction for defining bit lines for the memory cells of the device. The shielding layer is then utilized as a shielding mask for implementing an oxidation procedure, thereby forming field oxide layers over the surface of the substrate of the first conductivity type, whereby the shielding layer straddles the field oxide layers. Then the field oxide layers are utilized as the shielding mask for implanting impurities into the substrate, thereby forming the bit lines. The shielding layers then are utilized as the shielding mask for removing the field oxide layers while preserving the portions of the field oxide layer underneath the shielding layers, thereby forming trenches revealing the substrate. The shielding layers are then removed. An oxidation procedure is implemented for forming tunnel oxide layers in the trenches, an oxidation procedure further forming insulating layers over the bit lines. Floating gates are then formed over the surface of the tunnel oxide layers and the field oxide layers. An inter-gate dielectric layer is then formed over the floating gates. Finally, control gates for the device are formed over the inter-gate dielectric layers. The resulting floating gates have increased surface area, thus directly improving the coupling ratio.

REFERENCES:
patent: 5196361 (1993-03-01), Ong et al.
patent: 5208175 (1993-05-01), Choi et al.
patent: 5498556 (1996-03-01), Hong et al.
patent: 5498891 (1996-03-01), Sato
patent: 5502321 (1996-03-01), Matsushita

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