Methods and structures for expanding a memory operation...

Details Methods and structures for expanding a memory operation... Methods and structures for expanding a memory operation...

2006-06-21

2009-10-06

Tran, Michael T (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S230060

Reexamination Certificate

active

07599229

ABSTRACT:
Methods and structures are described for increasing a memory operation window in a charge trapping memory having a plurality of memory cells in which each memory cell is capable of storing multiple bits per memory cell. In a first aspect of the invention, a first method to increase a memory operation window in a two-bit-per-cell memory is described by applying a positive gate voltage, +Vg, to erase a memory cell to a negative voltage level. Alternatively, a negative gate voltage, −Vg, is applied to the two-bit-per-cell memory for erasing the memory cell to a negative voltage level. A second method to increase a memory operation window is to erase a memory cell to a voltage level that is lower than an initial voltage threshold level. These two erasing methods can be implemented either before a programming step (i.e., a pre-program erase operation) or after a programming step (i.e., a post-program erase operation).

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