Graphics processing system including at least three bus devices

Details Graphics processing system including at least three bus devices Graphics processing system including at least three bus devices

2005-04-25

2009-11-10

Wu, Xiao M (Department: 2628)

Computer graphics processing and selective visual display system

Computer graphic processing system

Plural graphics processors

C345S502000, C345S503000, C345S504000, C345S505000

Reexamination Certificate

active

07616207

ABSTRACT:
Multichip graphics processing subsystems include at least three distinct graphics devices (e.g., expansion cards) coupled to a high-speed bus (e.g., a PCI Express bus) and operable in a distributed rendering mode. One of the graphics devices provides pixel data to a display device, and at least one of the other graphics devices transfers the pixel data it generates to another of the devices via the bus to be displayed. Where the high-speed bus provides data transfer lanes, allocation of lanes among the graphics devices can be optimized.

REFERENCES:
patent: 5293480 (1994-03-01), Miller et al.
patent: 5434967 (1995-07-01), Tannenbaum et al.
patent: 5440682 (1995-08-01), Deering
patent: 5790130 (1998-08-01), Gannett
patent: 5841444 (1998-11-01), Mun
patent: 6023281 (2000-02-01), Grigor et al.
patent: 6078339 (2000-06-01), Meinerth et al.
patent: 6191800 (2001-02-01), Arenburg et al.
patent: 6259461 (2001-07-01), Brown
patent: 6317133 (2001-11-01), Root et al.
patent: 6362818 (2002-03-01), Gardiner et al.
patent: 6445391 (2002-09-01), Sowizral et al.
patent: 6469746 (2002-10-01), Maida
patent: 6473086 (2002-10-01), Morein et al.
patent: 6496187 (2002-12-01), Deering et al.
patent: 6570571 (2003-05-01), Morozumi
patent: 6621500 (2003-09-01), Alcorn et al.
patent: 6662257 (2003-12-01), Caruk et al.
patent: 6670958 (2003-12-01), Aleksic et al.
patent: 6724390 (2004-04-01), Dragony et al.
patent: 6747654 (2004-06-01), Laksono et al.
patent: 6781590 (2004-08-01), Katsura et al.
patent: 2001/0024205 (2001-09-01), Kishi et al.
patent: 2002/0030694 (2002-03-01), Ebihara et al.
patent: 2003/0128216 (2003-07-01), Walls et al.
patent: 2004/0075623 (2004-04-01), Hartman
patent: 2005/0012749 (2005-01-01), Gonzalez et al.
patent: 2005/0041031 (2005-02-01), Diard
patent: 2005/0088445 (2005-04-01), Gonzalez et al.
patent: 2007/0076006 (2007-04-01), Knepper et al.
patent: 0571969 (2003-05-01), None
PCI Express Base Specification Revision 1.0 (Apr. 29, 2002).
Whitman, “Dynamic Load Balancing for Parallel Polygon Rendering” IEEE Computer Graphics and Applications, IEEE Inc. New York, U.S. vol. 14, No. 4, pp. 41-48, Jul. 1, 1994.

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