Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2007-03-29
2009-08-18
Tran, Michael T (Department: 2827)
Static information storage and retrieval
Floating gate
Particular connection
C365S185240
Reexamination Certificate
active
07577031
ABSTRACT:
Variation in programming efficacy due to variation in time constants along a word line that spans across a memory plane is compensated by adjusting the bit line voltages across the plane to modify the programming rates. In this way, the variation in programming efficacy is substantially reduced during programming of a group of memory cells coupled to the word line. This will allow uniform optimization of programming across the group of memory cells and reduce the number of programming pulses required to program the group of memory cells, thereby improving performance. In one embodiment, during programming, the bit lines in a first half of the memory plane closer to a source of word line voltage is set to a first voltage and the bit lines in a second half of the memory plane further from the source of word line voltage is set to a second voltage.
REFERENCES:
patent: 4734886 (1988-03-01), Blankenship et al.
patent: 5070032 (1991-12-01), Yuan et al.
patent: 5095344 (1992-03-01), Harari et al.
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5313421 (1994-05-01), Guterman et al.
patent: 5315541 (1994-05-01), Harari et al.
patent: 5343063 (1994-08-01), Yuan et al.
patent: 5570315 (1996-10-01), Tanaka et al.
patent: 5595924 (1997-01-01), Yuan et al.
patent: 5661053 (1997-08-01), Yuan
patent: 5768192 (1998-06-01), Eitan
patent: 5812440 (1998-09-01), Suminaga et al.
patent: 5903495 (1999-05-01), Takeuchi et al.
patent: 6011725 (2000-01-01), Eitan
patent: 6046935 (2000-04-01), Takeuchi et al.
patent: 6222762 (2001-04-01), Guterman et al.
patent: 6337807 (2002-01-01), Futatsuyama et al.
patent: 7254064 (2007-08-01), Kim et al.
patent: 2002/0006068 (2002-01-01), Pochmuller
patent: 2002/0021543 (2002-02-01), Gogl et al.
patent: 2005/0232021 (2005-10-01), Lisart
patent: 2006/0203587 (2006-09-01), Li et al.
patent: 2006/0221693 (2006-10-01), Cernea et al.
patent: 2007/0223285 (2007-09-01), Wooldridge
patent: 2007/0253256 (2007-11-01), Aritome
patent: 2008/0056006 (2008-03-01), Jung et al.
patent: 06 150670 (1994-05-01), None
Eitan et al., “NROM: A Novel Localized Trapping 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Letters, vol. 21, No. 11, Nov. 2000, pp. 543-545.
Chan, “Methods for Improved Program-Verify Operations in Non-Volatile Memories,” U.S. Appl. No. 11/323,596, filed Dec. 29, 2005, 66 pages.
EPO/ISA, “Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority, or the Declaration,” corresponding International Patent Application No. PCT/US2008/056975, mailed on Jul. 8, 2008, 13 pages.
USPTO, “Notice of Allowance and Fee(s) Due,” corresponding U.S. Appl. No. 11/693,601 on Aug. 8, 2008, 18 pages.
Mokhlesi Nima
Mui Man Lung
Sekar Deepak Chandra
Davis , Wright, Tremaine, LLP
Sandisk Corporation
Tran Michael T
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