Semiconductor device and manufacturing method therefor

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

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C257S734000

Reexamination Certificate

active

07602063

ABSTRACT:
In a semiconductor having a multilayer wiring structure device on a semiconductor substrate, the multilayer wiring structure includes an interlayer insulating film having at least an organic siloxane insulating film. The organic siloxane insulating film has a relative dielectric constant of 3.1 or less, a hardness of 2.7 GPa or more, and a ratio of carbon atoms to silicon atoms between 0.5 and 1.0, inclusive. Further, the multilayer wiring structure may include an insulating layer having a ratio of carbon atoms to silicon atoms not greater than 0.1, the insulating layer being formed on the top surface of the organic siloxane insulating film as a result of carbon leaving the organic siloxane insulating film.

REFERENCES:
patent: 6358838 (2002-03-01), Furusawa et al.
patent: 6680541 (2004-01-01), Furusawa et al.
patent: 6740602 (2004-05-01), Hendriks et al.
patent: 2003/0162410 (2003-08-01), Huang et al.
patent: 2003/0201465 (2003-10-01), Ryuzaki et al.
patent: 2004/0033373 (2004-02-01), Rose et al.
patent: 2000-340569 (2000-12-01), None
patent: 2000-349083 (2000-12-01), None
patent: 2001-203200 (2001-07-01), None
patent: 2002-329718 (2002-11-01), None
Machine Translation of JP 2000-340569.
Machine Translation of JP 2002-329718.
M. Inohara, et al., “High Performance Copper and Low-k Interconnect Technology Fully Compatible to 90nm-node SOC Application (CMOS4)”, Technical Digest of 2002 IEDM, pp. 77-80.

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