Power and area efficient receiver circuit having constant...

Details Power and area efficient receiver circuit having constant... Power and area efficient receiver circuit having constant...

2005-06-23

2009-02-24

Pathak, Sudhanshu C (Department: 2611)

Pulse or digital communications

Receivers

C324S166000, C327S020000, C327S227000

Reexamination Certificate

active

07496154

ABSTRACT:
A hysteresis receiver containing two inverters and a logic controller. The inverters are implemented with threshold voltages equaling Vil and Vih, which together define the hysteresis window. The inverters receive the input signal and generate a respective inverted value. The logic controller propagates as output one of the two inverted values if the two inverted values are equal, and a prior value (corresponding to a previous sample) if the two inverted values are not equal. A receiver circuit with a hysteresis window defined by Vil and Vih, is obtained as a result.

REFERENCES:
patent: 5012207 (1991-04-01), Edwards
patent: 5079419 (1992-01-01), Falbel
patent: 6392446 (2002-05-01), Reasoner et al.
patent: 7068734 (2006-06-01), Bois et al.
patent: 7136429 (2006-11-01), Bois et al.

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