Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2007-08-13
2009-12-01
Williams, Alexander O (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257SE27009, C257SE23142, C257SE21580, C257SE21582, C257SE23141, C257SE29345, C257SE23010, C257SE23194, C257S506000, C257S773000, C257S633000, C257S401000, C257S776000, C257S579000, C257S288000, C257S368000, C257S388000, C257S183000, C257S197000, C257S762000, C257S766000, C257S374000
Reexamination Certificate
active
07626267
ABSTRACT:
Interconnections are formed over an interlayer insulating film which covers MISFETQ1formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.
REFERENCES:
patent: 4506434 (1985-03-01), Ogawa et al.
patent: 4916087 (1990-04-01), Tateoka et al.
patent: 4916514 (1990-04-01), Nowak
patent: 4935800 (1990-06-01), Taguchi
patent: 5010039 (1991-04-01), Ku et al.
patent: 5292689 (1994-03-01), Cronin
patent: 5321304 (1994-06-01), Rostoker
patent: 5323049 (1994-06-01), Motonami
patent: 5361234 (1994-11-01), Iwasa et al.
patent: 5441915 (1995-08-01), Lee
patent: 5441916 (1995-08-01), Motonami
patent: 5442236 (1995-08-01), Fukazawa
patent: 5459093 (1995-10-01), Kuroda et al.
patent: 5498565 (1996-03-01), Gocho et al.
patent: 5614445 (1997-03-01), Hirabayashi
patent: 5616761 (1997-04-01), Eguchi
patent: 5621241 (1997-04-01), Jain
patent: 5885856 (1999-03-01), Gilbert
patent: 5892277 (1999-04-01), Ikemizu
patent: 5929528 (1999-07-01), Kinugawa
patent: 6077784 (2000-06-01), Wu
patent: 6087733 (2000-07-01), Maxim
patent: 6103592 (2000-08-01), Levy et al.
patent: 6130139 (2000-10-01), Ukeda
patent: 6171976 (2001-01-01), Cheng
patent: 6261883 (2001-07-01), Koubuchi
patent: 6346736 (2002-02-01), Ukeda
patent: 6433438 (2002-08-01), Koubuchi
patent: 6614120 (2003-09-01), Sato et al.
patent: 6664642 (2003-12-01), Koubouchi
patent: 7102223 (2006-09-01), Kanaoka et al.
patent: 2002/0058411 (2002-05-01), Hasegawa
patent: 55-135837 (1980-10-01), None
patent: 01-149435 (1989-06-01), None
patent: 02-138757 (1990-05-01), None
patent: 2-504575 (1990-12-01), None
patent: 03-038043 (1991-02-01), None
patent: 03-071630-0 (1991-07-01), None
patent: 04-217328 (1992-08-01), None
patent: 05-267460 (1993-10-01), None
patent: 05-275527 (1993-10-01), None
patent: 06-069201 (1994-03-01), None
patent: 6-125013 (1994-05-01), None
patent: 06-151768 (1994-05-01), None
patent: 06-216332 (1994-08-01), None
patent: 06-326106 (1994-11-01), None
patent: 774175 (1995-03-01), None
patent: 923844 (1995-03-01), None
patent: 07092838 (1995-04-01), None
patent: 8-139043 (1996-05-01), None
patent: 08-288295 (1996-11-01), None
patent: 8314762 (1996-11-01), None
patent: 09-55421 (1997-02-01), None
patent: 09-181159 (1997-07-01), None
patent: 9181159 (1997-07-01), None
patent: 2802455 (1998-07-01), None
patent: 1994-0009350 (1994-10-01), None
patent: 1996-0000962 (1996-05-01), None
patent: 1997-011056 (1997-07-01), None
patent: 1996-0043102 (1998-12-01), None
patent: WO 90/03046 (1990-03-01), None
patent: WO 96/15552 (1996-05-01), None
Lee et al., An Optimized Densification of the Filled Oxide for Quarter Micron Shallow Trench Isolation (STI), 1996, Symposium on VLSI Technology Digest of Technical Papers, pp. 158-159.
Office Action of JP Appln. No. 2005-337967 with translation.
Koubuchi Yasushi
Moniwa Masahiro
Nagasawa Koichi
Takeda Toshifumi
Yamada Youhei
Antonelli, Terry Stout & Kraus, LLP.
Renesas Technology Corporation
Williams Alexander O
LandOfFree
Semiconductor integrated circuit device including wiring... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit device including wiring..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device including wiring... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4119837