Nonvolatile memory device having a block erase operation

Details Nonvolatile memory device having a block erase operation Nonvolatile memory device having a block erase operation

2006-12-19

2009-02-24

Le, Thong Q (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S185290, C365S200000, C365S230060

Reexamination Certificate

active

07495957

ABSTRACT:
According to a nonvolatile semiconductor memory device of the present invention, an address decode section130is provided in a block address decode circuit provided in a row decoder of a NAND-type flash memory device. The address decode section130has a selected block data storage section132composed of a latch circuit, a set section134, and a reset section136. The reset section136is composed of two nMOS transistors. Thus, defective block data and selected block data to be subjected to a multiple block erasure can be alternately stored in accordance with an operation without causing a complicated circuit structure or an increased chip size.

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