Semiconductor memory device and method of forming the same

Details Semiconductor memory device and method of forming the same Semiconductor memory device and method of forming the same

2007-06-26

2009-11-03

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Interconnection arrangements

C365S072000

Reexamination Certificate

active

07613022

ABSTRACT:
Example embodiments provide a semiconductor memory device and method of forming a semiconductor memory device that may equalize load due to a coupling capacitance between a line and a component signal when the line intersects the component signal in a memory cell array. A line may intersect a memory cell region between a transmitting point (A) and a receiving point (B) of a signal. A line between the transmitting point (A) and the receiving point (B) may be bent at two portions of each of bit lines. Because areas where the line and the bit lines extend parallel to each other may be equal in dimension at each bit line, coupling capacitances between the line and the bit lines may be equalized. The read characteristic may not be affected by the coupling capacitances.

REFERENCES:
patent: 5671173 (1997-09-01), Tomita
patent: 10-1999-0045010 (1999-06-01), None
patent: 10-2002-0078432 (2002-10-01), None
patent: 10-2007-0038233 (2007-04-01), None

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