Phase-locked loop circuit, delay locked loop circuit, timing...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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Details

Other Related Categories

C327S002000, C327S012000, C327S156000, C375S376000

Type

Reexamination Certificate

Status

active

Patent number

07492198

Description

ABSTRACT:
A PLL and DLL are designed such that the power consumption is reduced, the size is reduced, the band width of the locked loop is increased, and the reliability is improved. There are provided a phase comparator for measuring the value of a feedback signal in synchronism with an input signal and outputting a phase signal representing the lead or lag of the phase of the feedback signal, a counter for increasing by one the number of bits representing “H” in a control signal when the phase signal represents the lead of the phase or decreasing by one the number of bits representing “H” in the control signal when the phase signal represents the lag of the phase, and a ring oscillator for increasing the oscillation period when the number of bits representing “H” in the control signal increases or decreasing the oscillation period when the number of bits representing “H” decreases.

REFERENCES:
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patent: 5121014 (1992-06-01), Huang
patent: 5619148 (1997-04-01), Guo
patent: 5945856 (1999-08-01), Yanagiuchi
patent: 6194930 (2001-02-01), Matsuzaki et al.
patent: 6522175 (2003-02-01), Ueno et al.
patent: 6526109 (2003-02-01), Chang et al.
patent: 07-142997 (1995-06-01), None
patent: 11-065699 (1999-03-01), None
patent: 11-205131 (1999-07-01), None
patent: 2000-124779 (2000-04-01), None

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