Semiconductor memory device and method for erasing the same

Details Semiconductor memory device and method for erasing the same Semiconductor memory device and method for erasing the same

2007-12-04

2009-12-08

Lam, David (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185090, C365S185170, C365S185180, C365S185240

Reexamination Certificate

active

07630251

ABSTRACT:
A semiconductor memory device includes NAND cell units each having memory cells connected in series, select gate transistors disposed for coupling both ends of the NAND cell unit and dummy cells disposed between the select gate transistors and the memory cells neighbored to them. The dummy cells are set in a threshold voltage distribution higher than the erased threshold voltage of the memory cell by combination of a first program mode and a second program mode, the first program mode being for boosting the threshold voltage of the dummy cells with a program voltage applied while the second program mode is for boosting the threshold voltage of the dummy cells after reaching a certain threshold level under the condition that the threshold voltage increase is suppressed in comparison with the first program mode.

REFERENCES:
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patent: 7333367 (2008-02-01), Lee et al.
patent: 2006/0139997 (2006-06-01), Park et al.
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U.S. Appl. No. 11/857,091, filed Sep. 18, 2007, Koji Hosono.
Ki-Tae Park, et al., “Scalable Wordline Shielding Scheme Using Dummy Cell Beyond 40nm NAND Flash Memory for Eliminating Abnormal Disturb of Edge Memory Cell”, Extended Abstracts of the 2006 International Conference on Solid State Devices and Materials, 2006, pp. 298-299.

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