Plane decode/virtual sector architecture

Details Plane decode/virtual sector architecture Plane decode/virtual sector architecture

1996-09-24

1998-08-25

Hoang, Huan

Static information storage and retrieval

Floating gate

Particular biasing

36518533, 36518511, G11C 1604

Patent

active

057989680

ABSTRACT:
An EEPROM device having a plurality of flash EEPROM cells organized in right and left half memory planes each having right and left quad memory blocks is described along with corresponding control circuitry including erase circuitry for concurrently erasing selected addressable data sectors of the EEPROM device. Included in the erase circuitry are a plurality of erase voltage generating circuits, a corresponding plurality of switching circuitry, and switch control circuitry shared by the plurality of switching circuitry for controlling the selectable coupling of erase voltages generated by the erase voltage generating circuits to corresponding data sectors of the EEPROM device. To minimize the die size of an integrated circuit including such an EEPROM device, the switching circuitry is formed adjacent elongated gap regions containing contacts for connecting buried diffusion regions of the plurality of flash EEPROM cells to parallel running metal lines to reduce the effective resistance of the bit lines comprising the buried diffusion regions.

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