Digital clock smoothing apparatus and method

Details Digital clock smoothing apparatus and method Digital clock smoothing apparatus and method

2006-02-18

2009-11-03

Sheikh, Ayaz R (Department: 2419)

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

C375S372000

Reexamination Certificate

active

07613211

ABSTRACT:
A method for digital clock smoothing comprising: (A) inputting an asynchronous data stream having an asynchronous symbol rate into a two-port memory block; (B) accumulating a plurality of symbols of the asynchronous data stream in the two-port memory block for a predetermined time period; (C) computing an average symbol rate for the input asynchronous data stream; (D) generating a clock error signal equal to the difference between the average symbol rate of the input asynchronous data stream and a nominal output synchronous clock; (E) obtaining a smoothed symbol rate clock by using the error clock signal; and (F) generating an output smoothed data stream having the smoothed symbol rate clock.

REFERENCES:
patent: 4596026 (1986-06-01), Cease et al.
patent: 6381659 (2002-04-01), Proch et al.
patent: 6501809 (2002-12-01), Monk et al.
patent: 6714717 (2004-03-01), Lowe et al.

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