Three-dimensional package and method of making the same

Details Three-dimensional package and method of making the same Three-dimensional package and method of making the same

2007-10-30

2009-12-22

Clark, Jasmine J (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

For plural devices

C257S685000, C257S777000, C257SE25005, C257SE25020, C257SE25026

Reexamination Certificate

active

07635917

ABSTRACT:
The present invention relates to a three-dimensional package and method of making the same. The package includes a first substrate, a first chip, a second substrate, a second chip, a spacer, and a first molding compound. The first chip is electrically connected to the first substrate. The second substrate is electrically connected to the first substrate. The second chip is electrically connected to the second substrate. One end of the spacer is attached to the first chip, and the other end of the spacer is attached to the second chip. The first molding compound encapsulates the first substrate, the first chip, the second substrate, the second chip, and the spacer. In the present invention, the adhesion between the spacer and the second chip is enhanced, and the overall thickness of the three-dimensional package is reduced.

REFERENCES:
patent: 7101731 (2006-09-01), Karnezos
patent: 7250677 (2007-07-01), Lin

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