Method and system for multiprocessor emulation on a...

Data processing: structural design – modeling – simulation – and em – Emulation – Of instruction

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C703S023000

Reexamination Certificate

active

07496494

ABSTRACT:
A method (and system) for executing a multiprocessor program written for a target instruction set architecture on a host computing system having a plurality of processors designed to process instructions of a second instruction set architecture, includes representing each portion of the program designed to run on a processor of the target computing system as one or more program threads to be executed on the host computing system.

REFERENCES:
patent: 4564903 (1986-01-01), Guyette et al.
patent: 5440710 (1995-08-01), Richter et al.
patent: 5481684 (1996-01-01), Richter et al.
patent: 5574878 (1996-11-01), Onodera et al.
patent: 5574922 (1996-11-01), James
patent: 5619665 (1997-04-01), Emma
patent: 5668969 (1997-09-01), Fitch
patent: 5675762 (1997-10-01), Bodin et al.
patent: 5678032 (1997-10-01), Woods et al.
patent: 5751982 (1998-05-01), Morley
patent: 5768593 (1998-06-01), Walters et al.
patent: 5832205 (1998-11-01), Kelly et al.
patent: 5905998 (1999-05-01), Ebrahim et al.
patent: 5983012 (1999-11-01), Bianchi et al.
patent: 6031992 (2000-02-01), Cmelik et al.
patent: 6075937 (2000-06-01), Scalzi et al.
patent: 6075938 (2000-06-01), Bugnion et al.
patent: 6091897 (2000-07-01), Yates et al.
patent: 6134515 (2000-10-01), Skogby
patent: 6158049 (2000-12-01), Goodwin et al.
patent: 6189141 (2001-02-01), Benitez et al.
patent: 6289369 (2001-09-01), Sundaresan
patent: 6289419 (2001-09-01), Takahashi
patent: 6339752 (2002-01-01), Mann et al.
patent: 6341371 (2002-01-01), Tandri
patent: 6351844 (2002-02-01), Bala
patent: 6381682 (2002-04-01), Noel et al.
patent: 6430657 (2002-08-01), Mittal et al.
patent: 6463582 (2002-10-01), Lethin et al.
patent: 6480845 (2002-11-01), Egolf et al.
patent: 6539464 (2003-03-01), Getov
patent: 6728950 (2004-04-01), Davis et al.
patent: 6738974 (2004-05-01), Nageswaran et al.
patent: 6763328 (2004-07-01), Egolf et al.
patent: 6763452 (2004-07-01), Hohensee et al.
patent: 6915513 (2005-07-01), Duesterwald et al.
patent: 6961806 (2005-11-01), Agesen et al.
patent: 2002/0066086 (2002-05-01), Linden
patent: 2002/0104075 (2002-08-01), Bala et al.
patent: 2002/0147969 (2002-10-01), Lethin et al.
patent: 2002/0199172 (2002-12-01), Bunnell
patent: 2003/0093780 (2003-05-01), Freudenberger et al.
patent: 2003/0171907 (2003-09-01), Gal-On et al.
patent: 59-167756 (1984-09-01), None
patent: 62-163149 (1987-07-01), None
patent: 63-226740 (1988-09-01), None
patent: 07-271738 (1995-10-01), None
patent: 08-234981 (1996-09-01), None
patent: 08-272686 (1996-10-01), None
patent: 10-312298 (1998-11-01), None
patent: 2000-207233 (2000-07-01), None
patent: 2000-242512 (2000-09-01), None
patent: WO 95/16967 (1995-06-01), None
patent: WO 99/44131 (1999-09-01), None
“Java Multithreading” David Nelson-Gal et.al. , Jun. 1,1998, Java Developer's Journal, pp. 1-4, http://jdj.sys-con.com/read/35997.htm.
Lai et al.; Load balancing in distributed shared memory systems; IPCCC 1997., IEEE International; pp. 152-158.
Liang et al.; An effective selection policy for load balancing in software DSM; Parallel Processing, 2000. Proceedings. 2000 International Conference on; Aug. 2000 pp. 105-112.
Bala, V., et al., “Dynamo: A Transparent Dynamic Optimization System”,Conference on Programming Language Design and Implementation, 2000, pp. 1-12.
Burke, M.G., et al., “The Jalapeno Dynamic Optimizing Compiler for JavaTM”,IBM Thomas J. Watson Research Center Technical Paper, Mar. 1999, 13 pages (published 1999 ACM Java Grande Conference Proceedings, San Francisco, CA, Jun. 12-14,1999).
Ball, T., et al., “Efficient Path Profiling”,IEEE Proceedings of MICRO-29, Dec. 2-4, 1996, pp. 1-12.
“Computer Dictionary”, Third Edition, Microsoft Press, 1997, excerpts including p. 467.
IBM, “Low-Synchronization Translation Lookaside Buffer Consistency Algorithm” (ID NB9011428), IBM Technical Disclosure Bulletin, Nov. 1990 vol. 33 Issue 6B p. 428-433.
Hoogerbrugge et al., “Pipelined Java Virtual Machine Interpreters”, 2000 (15 pages).
University of Queensland, “The University of Queensland Binary Translator (UQBT) Framework”, 2001, 326 page (34 pages extracted). Online version can be obtained at <www.experimentalstuff.com/Technologies/uqbt/uqbt.pdf>.
Julian Brown, “ARMphetamine—A Dynamically Recompiling ARM Emulator”, May 2000, 97 pages (36 pages extracted). Online version can be obtained at <http://armphetamine.sourceforge.net/diss.ps>.
“A framework for remote dynamic program optimization”, M. J. Voss and R. Eigenmann, Proceedings of the ACM SIGPLAN workshop on Dynamic and adaptive compilation and optimization table of contents pp. 32-40, 2000, pp. 32-40, ISBN: 1-58113-241-7.
“Using Annotation to Reduce Dynamic Optimiation Time”, C. Krintz and B. Calder, 2001 ACM ISBN-158113-414-2/01/06, pp. 156-167.
“Prototype real-Time monitor: Design” R. Van Scoy et al., Technical Report CMU/SEI-87-TR-038 ESD-TR-87-201, Nov. 1987.
Magnusson, P.S., “A Design for Efficient Simulation of a Multiprocessor”, Proceedings of the First International Workshop on Modeling, Analysis, and simulation of Computer and Telecommunication Systems (MASCOTS), La Jolla, Ca Jan. 1993, pp. 3 69-78.
Lamport, L., “How to Make a Multiprocessor Computer that Correctly Executes Multiprocess Programs”, IEEE Transactions on Computers, C-28 Sep. 9, 1979, pp. 690-691.
Adve, S., et al., “Shared Memory Consistency Models: A Tutorial”, IEEE Computer, vol. 29, No. 12, Dec. 1996, pp. 66-76.
Herrod, S.A., “Using Complete Machine Simulation to Understand Computer System Behavior”, Ph.D. Thesis, Stanford University, Feb. 1998.
Nichols, B., et al., “Pthreads Programming: A POSIX Standard for Better Multiprocessing” (O'Reilly Nutshell), Sep. 1996.
May, C., “Mimic: A Fast System/370 Simulator”, Proceedings of the Object Oriented Programming Systems Languages and Applications Conference (OOPSLA), Orlando, FL, Oct. 4-8, 1987, Special Issue of Sigplan Notices, Dec. 1987, vol. 22, No. 7, Jun. 24.
Turley, J., “Alpha Run x86 Code with FX!32”, Microprocessor Report, Mar. 5,1996.
Wikipedia entries and revision histories of “Memory coherence”, Consistency model, “Weak consistency”, “Emulator”, “Virtual machines”, and Simulation, http://en.wikipedia.org. accessed Feb. 21, 2007, 21 pages., date of publication not provided.
Department of Defense, “DoD” Modeling and Simnulation (M&S) Glossary, Jan. 1998, 175 pages.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and system for multiprocessor emulation on a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and system for multiprocessor emulation on a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for multiprocessor emulation on a... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4100822

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.