Fully synchronous DLL with architected update window

Details Fully synchronous DLL with architected update window Fully synchronous DLL with architected update window

2006-07-28

2009-02-17

Wells, Kenneth B (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

Reexamination Certificate

active

07492199

ABSTRACT:
The invention provides for a method for architecting a delay locked loop clock signal comprising: providing at least one clock signal to a clock signal splitter; alternately outputting the at least one clock signal from the clock signal splitter on at least two matched delay lines; alternately propagating the clock signal down each of the at least two matched delay lines; specifying a delay period for each of the matched delay lines with a control signal; updating said the two matched delay lines with the control signal when a fixed update window is always present on the matched delay lines; and distributing the clock signal to synchronously update the at least two matched delay lines, wherein no transitions are present in the fixed update window on the matched delay lines. Collect clock pulse outputs from the delay lines and reconstruct a delayed version of the input clock.

REFERENCES:
patent: 5604775 (1997-02-01), Saitoh et al.
patent: 6856415 (2005-02-01), Simchik et al.
patent: 7061287 (2006-06-01), Jeon
patent: 2004/0130366 (2004-07-01), Lin et al.
patent: 2005/0093597 (2005-05-01), Kwak

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