Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2006-11-21
2009-08-11
Dang, Phuc T (Department: 2892)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S433000, C438S438000, C257S217000, C257SE21549
Reexamination Certificate
active
07572712
ABSTRACT:
Embodiments for FET devices with stress on the channel region by forming stressor regions under the source/drain regions or the channel region and forming a selective strained Si using lateral epitaxy over the stressor regions. In a first example embodiment, a lateral epitaxial layer is formed over a stressor region under a channel region of an FET. In a second example embodiment, a lateral S/D epitaxial layer is formed over S/D stressor region under the source/drain regions of an FET. In a third example embodiment, both PFET and NFET devices are formed. In the PFET device, a lateral S/D epitaxial layer is formed over S/D stressor region under the source/drain regions. In the NFET device, the lateral epitaxial layer is formed over a stressor region under a channel region of the NFET.
REFERENCES:
patent: 6274913 (2001-08-01), Brigham
patent: 6563152 (2003-05-01), Roberds
patent: 6690043 (2004-02-01), Usuda
patent: 6717216 (2004-04-01), Doris
patent: 6841430 (2005-01-01), Sugawara
patent: 6884667 (2005-04-01), Doris
patent: 6900502 (2005-05-01), Ge
patent: 7364975 (2008-04-01), Culmsee et al.
patent: 2002/0074598 (2002-06-01), Doyle
patent: 2002/0190344 (2002-12-01), Michejda
patent: 2003/0022412 (2003-01-01), Higgins et al.
patent: 2004/0026765 (2004-02-01), Currie et al.
patent: 2004/0209479 (2004-10-01), Heo et al.
patent: 2005/0051841 (2005-03-01), Leedy
patent: 2005/0085022 (2005-04-01), Chidambarrao
patent: 2005/0139929 (2005-06-01), Rost
patent: 2005/0139930 (2005-06-01), Chidambarrao
patent: 2005/0145837 (2005-07-01), Chan
patent: 2007/0132056 (2007-06-01), Williams
patent: 2007/0196996 (2007-08-01), Han et al.
Chong Yung Fu
Holt Judson R.
Luo Zhijiong
Chartered Semiconductor Manufacturing Ltd.
Dang Phuc T
Horizon IP Pte Ltd
International Business Machines Corporation (IBM)
LandOfFree
Method to form selective strained Si using lateral epitaxy does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method to form selective strained Si using lateral epitaxy, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method to form selective strained Si using lateral epitaxy will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4097852