Power semiconductor device architecture for output...

Details Power semiconductor device architecture for output... Power semiconductor device architecture for output...

2008-01-10

2009-10-20

Paladini, Albert W (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

With specific current responsive fault sensor

C361S091100

Reexamination Certificate

active

07606015

ABSTRACT:
A power semiconductor device is provided with an output transistor, a load control circuit, and a pull-up circuit. The output transistor is connected between a power supply terminal provided to receive a power supply voltage and an output terminal to be connected with a load. The load control circuit is adapted to feed the gate voltage to the gate of the output transistor. When short-circuiting of the load occurs, the load control circuit stops feeding the gate voltage to the output transistor. The pull-up circuit is connected between the power supply terminal and the gate of the output transistor. The pull-up circuit is adapted to discharge electric charges on said gate of said output transistor, when short-circuiting of the load occurs with the voltage level on the power supply terminal lowered than the power supply voltage.

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patent: 6087877 (2000-07-01), Gonda et al.
patent: 7129759 (2006-10-01), Fukami
patent: 7339775 (2008-03-01), Kimura
patent: 2002/0079944 (2002-06-01), Sander
patent: 2005/0068705 (2005-03-01), Nakahara
patent: 2005/0088216 (2005-04-01), Arndt et al.
patent: 2001-160746 (2001-06-01), None
patent: 2006-086507 (2006-03-01), None

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