Nonvolatile semiconductor memory device and nonvolatile...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185280, C365S185170, C365S185090

Reexamination Certificate

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07613048

ABSTRACT:
A nonvolatile semiconductor memory device including a memory cell array including a plurality of electrically rewritable nonvolatile memory cells arranged in series, the memory cell storing data using a plurality of threshold levels, a threshold level storage section storing a programming method switch threshold level on which a first programming method and a second programming method are switched, a comparison circuit comparing the programming method switch threshold level with a programming data threshold level and outputting a comparison result, a control signal generation circuit setting the first programming method or the second programming method based on the comparison result and outputting a control signal corresponding to the first programming method or the second programming method and a voltage generation circuit generating a programming voltage and an intermediate voltage which are applied to the memory cell based on the control signal.

REFERENCES:
patent: 6134148 (2000-10-01), Kawahara et al.
patent: 6643188 (2003-11-01), Tanaka et al.
patent: 6958936 (2005-10-01), Quader et al.
patent: 7173859 (2007-02-01), Hemink
patent: 2007/0081388 (2007-04-01), Joo
patent: 2003-196988 (2003-07-01), None
patent: 1020070039720 (2007-04-01), None

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