Parallel multiplier

Details Parallel multiplier Parallel multiplier

1995-09-11

1998-08-25

Malzahn, David H.

Boots, shoes, and leggings

G06F 752

Patent

active

057989567

ABSTRACT:
An improved parallel multiplier capable of operating an addition operation by connecting a plurality of dividers sequentially, thus providing more simple circuit and reducing operating time thereof, which includes NXM AND-gates each for ANDing each multiplier bit ranging from a least significant bit to a most significant bit with each multiplicand bit in case of multiplying "N" multiplicand bits and "M" multiplier bits and for performing a partial multiplication and for outputting a least significant bit as a result of the multiplication; and a plurality of input-bits dividers, having 2-, 3-, and 4-input-bits dividers, for receiving an output bit of a corresponding location among a rearranged output bit and a quotient bit outputted from a proceeding input bit in case that the output bits of the AND-gates is shifted to the left by a bit in accordance with a conventional binary multiplication method and for outputting a quotient bit and a remaining bit corresponding to each bit of a multiplication result.

REFERENCES:
patent: 3346729 (1967-10-01), Dell et al.
patent: 3506817 (1970-04-01), Winder
patent: 3691359 (1972-09-01), Dell et al.
patent: 3900724 (1975-08-01), McIver
patent: 3914589 (1975-10-01), Gaskill, Jr. et al.
patent: 3950636 (1976-04-01), Dao
patent: 4369500 (1983-01-01), Fette

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