Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2007-02-02
2009-02-03
Lindsay, Jr., Walter L (Department: 2812)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S106000, C438S111000, C257S666000, C257S676000, C257SE21499
Reexamination Certificate
active
07485498
ABSTRACT:
Efficient utilization of space in a laterally-conducting semiconductor device package is enhanced by creating at least one supplemental downbond pad portion of the diepad for receiving the downbond wire from the ground contact of the device. The supplemental diepad portion may occupy area at the end or side of the package formerly occupied by non-integral leads. By receiving the substrate downbond wire, the supplemental diepad portion allows a greater area of the main diepad to be occupied by a die having a larger area, thereby enhancing space efficiency of the package.
REFERENCES:
patent: 5289344 (1994-02-01), Gagnon et al.
patent: 5631809 (1997-05-01), Takagi et al.
patent: 6710432 (2004-03-01), Pasqualini
patent: 2003/0151123 (2003-08-01), Huschka et al.
Chia Anthony
Harnden James
Lam Allen K.
Weibing Chu
Williams Richard K.
Ahmadi Mohsen
GEM Services, Inc.
Lindsay, Jr. Walter L
Townsend and Townsend / and Crew LLP
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