Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material
Reexamination Certificate
2006-07-07
2009-10-20
Nguyen, Khiem D (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
C438S637000, C257SE21023, C257SE23141, C977S762000
Reexamination Certificate
active
07605066
ABSTRACT:
A method realizes an electric connection between a nanometric circuit and standard electronic components. The method includes: providing, above a semiconductor substrate, a seed having a notched wall substantially perpendicular to the substrate, the wall having n recesses spaced apart from one another; and realizing n conductive nanowires alternated with insulating nanowires. Each realization of a conductive nanowire fills a corresponding recess by a respective elbow-like portion of the conductive nanowire, and partially fills the other recesses by respective notched profile portions, thereby forming the nanometric circuit. The method forms, above the nanometric circuit, an insulating layer; opens, in the insulating layer, n windows respectively corresponding with the recesses, thereby exposing the respective elbow-like portions; and realizes, above the insulating layer, n conductive dies addressed towards the standard electronic components and respectively overlapping the windows, thereby forming n contacts realizing the electric connection.
REFERENCES:
patent: 4994410 (1991-02-01), Sun et al.
patent: 5963827 (1999-10-01), Enomoto et al.
patent: 6128214 (2000-10-01), Kuekes et al.
patent: 6256767 (2001-07-01), Kuekes et al.
patent: 6268657 (2001-07-01), Watanabe et al.
patent: 6548881 (2003-04-01), Blish et al.
patent: 6984294 (2006-01-01), Friedemann et al.
patent: 7230286 (2007-06-01), Cohen et al.
patent: 2003/0085439 (2003-05-01), Gudesen et al.
patent: 2005/0052894 (2005-03-01), Segal et al.
Michael D. Austin et al., “6 nm half-pitch lines and 0.04 μm2static random access memory patterns by nanoimprint lithography,”Nanotechnology, vol. 16 (2005), pp. 1058-1061.
G.F. Cerofolini et al., “A hybrid approach to nanoelectronics,”Nanotechnology, vol. 16 (2005), pp. 1040-1047.
André DeHon et al., “Stochastic Assembly of Sublithographic Nanoscale Interfaces,”IEEE Transactions on Nanotechnology. vol. 2, No. 3, Sep. 2003, pp. 165-174.
Nicholas A. Melosh et al., “Ultrahigh-Density Nanowire Lattices and Circuits,”Science, vol. 300, Apr. 4, 2003, pp. 112-115.
Sachin R. Sonkusale et al., “Fabrication of wafer scale, aligned sub-25 nm nanowire and nanowire templates using planar edge defined alternate layer process,”Physica E, vol. 28 (2005), pp. 107-114.
Cerofolini Gianfranco
Mascolo Danilo
Jorgenson Lisa K.
Nguyen Khiem D
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
Tarleton E. Russell
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