Semiconductor memory device capable of controlling clock...

Details Semiconductor memory device capable of controlling clock... Semiconductor memory device capable of controlling clock...

2006-07-19

2009-02-10

Tran, Andrew Q (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S233130, C365S194000, C365S227000, C365S230020, C327S156000, C327S158000, C327S161000, C327S149000, C327S152000, C327S153000

Reexamination Certificate

active

07489587

ABSTRACT:
Some embodiments of the invention include a delay locked loop having a delay line for delaying an input signal. The input signal is generated from a first signal. A delay controller controls the delay line to adjust the timing relationship between the first signal and an internal signal. The delay locked loop also includes cycle control circuitry for controlling the cycle time of the signal entering the delay line and the cycle time of the signal exiting the delay line.

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