Method and apparatus for providing address-size backward compati

Details Method and apparatus for providing address-size backward compati Method and apparatus for providing address-size backward compati

1996-10-22

1999-06-15

Moore, David K.

3954211, 39542104, 39542107, G06F 1206, G06F 926

Patent

active

059130504

ABSTRACT:
This invention overcomes the address size backward compatibility problem by first subtracting the segment base address from the linear destination address of a branch instruction to generate a virtual destination address. It is assumed that the branch instruction destination address is n bits long with m most significant bits. It is desired to provide backward compatibility in the n-bit processor for branch instruction code written for processors utilizing instruction address fields of size (n-m) bits. After obtaining the virtual address, if any of the m most significant bits are non-zero, then those m bits are set to zero to thereby generate a corrected virtual address. If such a compatibility correction is necessary, then a clear signal is asserted to flush all state of the processor that resulted from instructions being fetched after the branch instruction was fetched. The corrected virtual address is added back to the segment base address to generate a corrected linear address. The next instruction is fetched at the corrected linear address.

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