Method of forming a multiple fin-pillar capacitor for a high den

Details Method of forming a multiple fin-pillar capacitor for a high den Method of forming a multiple fin-pillar capacitor for a high den

1998-08-15

1999-05-25

Bowers, Charles

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

438396, 438253, 438255, H01L 2120

Patent

active

059077824

ABSTRACT:
The present invention is a method of manufacturing a high density capacitor for use in semiconductor memories. High etching selectivity between BPSG (borophosphosilicate glass) and CVD-oxide (chemical vapor deposition oxide) is used to fabricate a capacitor with a plurality of horizontal fins. First, a nitride layer is formed on a semiconductor substrate. A stacked layer consists of BPSG and silicon oxide formed on the nitride layer. Then a contact hole is formed in the stacked layer and the nitride layer. A highly selective etching is then used to etch the BPSG sublayers of the stacked layer. Next, a first polysilicon layer is formed in the contact hole and the stacked layer, subsequently, a dielectric layer is formed on the first polysilicon layer. Then, undoped hemispherical-grain silicon (HSG--Si) is formed on the dielectric layer. Next, a portion of the dielectric layer is etched using the HSG--Si layer as a hard mask to expose a portion of the first polysilicon layer. A second polysilicon layer is formed on the HSG--Si layer and the exposed first polysilicon layer. An etching back or CMP is used for planarization. Then photolithography and etching process is used to define the storage node. Next the stacked layer is removed by BOE solution. A dielectric film is then formed along the surface of the first and second polysilicon layer. Finally, a third polysilicon layer is formed on the dielectric film. Thus, a capacitor with multiple horizontal fins and vertical pillars is formed.

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