Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2007-12-19
2009-06-02
Mai, Son L (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185110, C365S208000
Reexamination Certificate
active
07542348
ABSTRACT:
A bipolar segment read circuit is applied for reading NOR flash memory such that cell current is converted to voltage by discharging bit line, which voltage is amplified by the bipolar segment read circuit, and then the voltage difference is converted to time difference by a block read circuit. In this manner, a reference signal is generated by reference cells storing low threshold data, which signal is delayed by a tunable delay circuit for generating a locking signal. Thus the locking signal effectively rejects latching high threshold data in latch circuits because high threshold data is arrived later. Furthermore, by adopting multi-divided bit line architecture, discharging time of bit line is reduced. And the memory cell can be formed from single crystal silicon or thin film polysilicon because the memory cell only drives lightly loaded bit line, even though thin film transistor can flow relatively low current, which realizes multi-stacked memory.
REFERENCES:
patent: 4237472 (1980-12-01), Hollingsworth
patent: 5371703 (1994-12-01), Miyamoto
patent: 5422854 (1995-06-01), Hirano et al.
patent: 5862077 (1999-01-01), Briner
patent: 5973957 (1999-10-01), Tedrow
patent: 6888770 (2005-05-01), Ikehashi
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